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cy29350 2.5 v or 3.3 v, 200-mhz, 9-output clock driver cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07474 rev. *c revised april 12, 2011 2.5 v or 3.3 v, 200-mhz, 9-output clock driver features output frequency range: 25 mhz to 200 mhz input frequency range: 6.25 mhz to 31.25 mhz 2.5 v or 3.3 v operation split 2.5 v/3.3 v outputs 2.5% max output duty cycle variation nine clock outputs: drive up to 18 clock lines two reference clock inputs: xtal or lvcmos 150-ps max output-output skew phase-locked loop (pll) bypass mode spread aware? output enable/disable pin-compatible with mpc9350 industrial temperature range: ?40 c to +85 c 32-pin 1.0 mm tqfp package functional description the cy29350 is a low-voltage high-performance 200-mhz pll-based clock driver designed for high speed clock distribution applications. the cy29350 features xtal and lvcmos reference clock inputs and provides nine outputs partition ed in four banks of 1, 1, 2, and 5 outputs. bank a divides the vco output by 2 or 4 while the other banks divide by 4 or 8 per sel(a:d) settings, see . these dividers allow output to input ra tios of 16:1, 8: 1, 4:1, and 2:1. each lvcmos compatible output can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. the pll is ensured stable given that the vco is configured to run between 200 mhz to 500 mhz. this allows a wide range of output frequencies from 25 mhz to 200 mhz. the internal vco is running at multiples of the input reference clock set by the feedback divider, see ta b l e 1 . when pll_en is low, pll is bypassed and the reference clock directly feeds the output dividers. this mode is fully static and the minimum input clock frequency specification does not apply. block diagram osc phase detector vco 200 - 500mhz lpf ????????? ??????? ??????? ??????? ??????? qa qb qc0 qc1 qd0 qd1 qd2 qd3 qd4 sela pll_en tclk ref_sel xin xout fb_sel selb selc oe# seld [+] feedback
cy29350 document number: 38-07474 rev. *c page 2 of 13 contents pin configuration ............................................................. 3 pin definitions .................................................................. 4 absolute maximum conditions ....................................... 5 dc electrical specifications ............................................ 6 dc electrical specifications ............................................ 6 ac electrical specifications ............................................ 7 ac electrical specifications ............................................ 8 ordering information ...................................................... 10 ordering code definitions ......................................... 10 package drawing and dimension ................................. 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy29350 document number: 38-07474 rev. *c page 3 of 13 pin configuration cy29350 ref_sel pll_en tclk vss qa vddqb qb vss xin oe# vdd qd4 vss qd3 vddqd qd2 qc0 vddqc qc1 vss qd0 vddqd qd1 vss avdd fb_sel sela selb selc seld avss xout 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 [+] feedback
cy29350 document number: 38-07474 rev. *c page 4 of 13 pin definitions [1] pin name i/o type description 8xoutoanalog oscillator output . connect to a crystal. 9xinianalog oscillator input . connect to a crystal. 30 tclk i, pd lvcmos lvcmos/lvttl reference clock input 28 qa o lvcmos clock output bank a 26 qb o lvcmos clock output bank b 22, 24 qc(1:0) o lvcmos clock output bank c 12, 14, 16, 18, 20 qd(4:0) o lvcmos clock output bank d 2 fb_sel i, pd lvcmos internal feedback select input . see ta b l e 1 . 10 oe# i, pd lvcmos output enable/disable input . see ta b l e 2 . 31 pll_en i, pu lvcmos pll enable/disable input . see table 2 . 32 ref_sel i, pd lvcmos reference select input . see ta b l e 2 . 3, 4, 5, 6 sel(a:d) i, pd lvcmos frequency select input, bank (a:d) . see ta b l e 2 . 27 vddqb supply vdd 2.5 v or 3.3 v power supply for bank b output clock [2, 3] 23 vddqc supply vdd 2.5 v or 3.3 v power supply for bank c output clocks [2, 3] 15, 19 vddqd supply vdd 2.5 v or 3.3 v power supply for bank d output clocks [2, 3] 1 avdd supply vdd 2.5 v or 3.3 v power supply for pll [2, 3] 11 vdd supply vdd 2.5 v or 3.3 v power supply for core, inputs, and bank a output clock [2, 3] 7 avss supply ground analog ground 13, 17, 21, 25, 29 vss supply ground common ground table 1. frequency table fb_sel feedback divider vco input frequency range (avdd = 3.3 v) input frequency range (avdd = 2.5 v) 0 ? 32 input clock * 32 6.25 mhz to 15.625 mhz 6.25 mhz to 11.875 mhz 1 ? 16 input clock * 16 12.5 mhz to 31.25 mhz 12.5 mhz to 23.75 mhz table 2. function table control default 0 1 ref_sel 0 xtal tclk pll_en 1 bypass mode, pll disabled. the input clock connects to the output dividers pll enabled. the vco output connects to the output dividers oe# 0 outputs enabled outputs disabled (three-state) fb_sel 0 feedback divider ? 32 feedback divider ? 16 sela 0 ? 2 (bank a) ? 4 (bank a ) selb 0 ? 4 (bank b) ? 8 (bank b) selc 0 ? 4 (bank c) ? 8 (bank c) seld 0 ? 4 (bank d) ? 8 (bank d) notes 1. pu = internal pull-up, pd = internal pull-down. 2. a 0.1 ? f bypass capacitor should be placed as clos e as possible to each positive power pin (< 0.2?). if these bypass capacitors are no t close to the pins their high frequency filtering characteristics will be c ancelled by the lead indu ctance of the traces. 3. avdd and vdd pins must be connected to a power supply level that is at least equal or higher than that of vddqb, vddqc, and v ddqd output power supply pins. [+] feedback
cy29350 document number: 38-07474 rev. *c page 5 of 13 absolute maximum conditions parameter description condition min max unit v dd dc supply voltage ?0.3 5.5 v v dd dc operating voltage functional 2.375 3.465 v v in dc input voltage relative to v ss ?0.3 v dd + 0.3 v v out dc output voltage relative to v ss ?0.3 v dd + 0.3 v v tt output termination voltage ? v dd ? 2v lu latch up immunity functional 200 ? ma r ps power supply ripple ripple frequency < 100 khz ? 150 mvp-p t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional ?40 +85 c t j temperature, junction functional ? +150 c ? jc dissipation, junction to case functional ? 42 c/w ? ja dissipation, junction to ambient functional ? 105 c/w esd h esd protection (human body model) 2000 ? volts fit failure in time manufacturing test 10 ppm [+] feedback
cy29350 document number: 38-07474 rev. *c page 6 of 13 dc electrical specifications (v dd = 2.5 v 5%, t a = ?40 c to +85 c) parameter description condition min typ max unit v il input voltage, low lvcmos ? ? 0.7 v v ih input voltage, high lvcmos 1.7 ? v dd + 0.3 v v ol output voltage, low [4] i ol = 15ma ? ? 0.6 v v oh output voltage, high [4] i oh = ?15ma 1.8 ? ? v i il input current, low [5] v il = v ss ? ? ?100 ? a i ih input current, high [5] v il = v dd ? ? 100 ? a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 7 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 180 ? ma outputs loaded @ 200 mhz ? 210 ? c in input pin capacitance ? 4 ? pf z out output impedance 14 18 22 ? dc electrical specifications (v dd = 3.3 v 5%, t a = ?40 c to +85 c) parameter description condition min typ max unit v il input voltage, low lvcmos ? ? 0.8 v v ih input voltage, high lvcmos 2.0 ? v dd + 0.3 v v ol output voltage, low [4] i ol = 24 ma ? ? 0.55 v i ol = 12 ma ? ? 0.30 v oh output voltage, high [4] i oh = ?24 ma 2.4 ? ? v i il input current, low [5] v il = v ss ?? ? ?100 ? a i ih input current, high [5] v il = v dd ? ? 100 ? a i dda pll supply current avdd only ? 5 10 ma i ddq quiescent supply current all vdd pins except avdd ? ? 7 ma i dd dynamic supply current outputs loaded @ 100 mhz ? 270 ? ma outputs loaded @ 200 mhz ? 300 ? c in input pin capacitance ? 4 ? pf z out output impedance 12 15 18 ? notes 4. driving one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, each output drives up to two 50 ? series terminated transmission lines. 5. inputs have pull-up or pull-down resistors that affect the input current. [+] feedback
cy29350 document number: 38-07474 rev. *c page 7 of 13 ac electrical specifications (v dd = 2.5 v 5%, t a = ?40 c to +85 c) [6] parameter description condition min typ max unit f vco vco frequency 200 ? 380 mhz f in input frequency ? 16 feedback 12.5 ? 23.75 mhz ? 32 feedback 6.25 ? 11.87 bypass mode (pll_en = 0) 0 ? 200 f xtal crystal oscillator frequency 10 ? 23.75 mhz f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.7 v to 1.7 v ? ? 1.0 ns f max maximum output frequency ? 2 output 100 ? 190 mhz ? 4 output 50 ? 95 ? 8 output 25 ? 47.5 dc output duty cycle f max < 100 mhz 47.5 ? 52.5 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0.6v to 1.8v 0.1 ? 1.0 ns t sk(o) output-to-output skew ? ? 150 ps t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (?3 db) ? 16 feedback ? 0.7?0.9 ? mhz ? 32 feedback ? 0.6?0.8 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 250 t jit(per) period jitter same frequency ? ? 100 ps multiple frequencies ? ? 175 t lock maximum pll lock time ? ? 1 ms note 6. ac characteristics apply for parallel output termination of 50 ?? to v tt . parameters are guaranteed by characterization and are not 100% tested. [+] feedback
cy29350 document number: 38-07474 rev. *c page 8 of 13 ac electrical specifications (v dd = 3.3 v 5%, t a = ?40 c to +85 c) [7] parameter description condition min typ max unit f vco vco frequency 200 ? 500 mhz f in input frequency ? 16 feedback 12.5 ? 31.25 mhz ? 32 feedback 6.25 ? 15.625 bypass mode (pll_en = 0) 0 ? 200 f xtal crystal oscillator frequency 10 ? 25 mhz f refdc input duty cycle 25 ? 75 % t r , t f tclk input rise/falltime 0.8 v to 2.0 v ? ? 1.0 ns f max maximum output frequency ? 2 output 100 ? 200 mhz ? 4 output 50 ? 125 ? 8 output 25 ? 62.5 dc output duty cycle f max < 100 mhz 47.5 ? 52.5 % f max > 100 mhz 45 ? 55 t r , t f output rise/fall times 0.8 v to 2.4 v 0.1 ? 1.0 ns t sk(o) output-to-output skew banks at same voltage ? ? 150 ps tsk(b) bank-to-bank skew banks at different voltages ? ? 350 ps t plz, hz output disable time ? ? 10 ns t pzl, zh output enable time ? ? 10 ns bw pll closed loop bandwidth (?3 db) ? 16 feedback ? 0.7?0.9 ? mhz ? 32 feedback ? 0.6?0.8 ? t jit(cc) cycle-to-cycle jitter same frequency ? ? 150 ps multiple frequencies ? ? 250 t jit(per) period jitter same frequency ? ? 100 ps multiple frequencies ? ? 150 t lock maximum pll lock time ? ? 1 ms note 7. ac characteristics apply for parallel output termination of 50 ?? to v tt . parameters are guaranteed by characterization and are not 100% tested. [+] feedback
cy29350 document number: 38-07474 rev. *c page 9 of 13 pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm figure 1. ac test reference for v dd = 3.3 v / 2.5 v vdd gnd vdd/2 t p t0 dc = tp / t0 x 100% figure 2. output duty cycle (dc) t sk(o) vdd gnd vdd/2 vdd gnd vdd/2 figure 3. output -to-output skew , t sk(o) table 3. suggested oscillator crystal parameters characteristic symbol conditions min typ max units frequency tolerance t c ? ? 100 ppm frequency temperature stability t s (t a ?10 +60 c) ? ? 00 ppm aging t a first three years @ 25 c ? ? 5 ppm/yr load capacitance c l crystal?s rated load ? 20 ? pf effective series resistance r esr ?4080 ? [+] feedback
cy29350 document number: 38-07474 rev. *c page 10 of 13 ordering code definitions package drawing and dimension figure 4. 32-pin tqfp 7 x 7 x 1.0 mm a3210 ordering information part number package type product flow cy29350axi 32-pin tqfp, pb-free i ndustrial, ?40 c to +85 c cy29350axit 32-pin tqfp ? tape and reel , pb-free industrial, ?40 c to 85 c t = tape and reel temperature range: x = c or i c = commercial; i = industrial package type: ax = 32-pin tqfp base device part number company id: cy = cypress cy 29350 ax x t 51-85063 *c [+] feedback
cy29350 document number: 38-07474 rev. *c page 11 of 13 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor esd electrostatic discharge i/o input/output lvcmos low voltage complementary metal oxide semiconductor lvttl low voltage transistor-transistor logic pll phase-locked loop tqfp thin quad flat pack vco voltage-controlled oscillator symbol unit of measure c degree celsius hz hertz khz kilo hertz mhz mega hertz f micro farads a micro amperes mm milli meter ma milli amperes ms milli seconds ns nano seconds ? ohms % percent pf pico farads ppm parts per million ps pico seconds kv kilo volts mv milli volts vvolts wwatts [+] feedback
cy29350 document number: 38-07474 rev. *c page 12 of 13 document history page document title:cy29350 2.5 v or 3.3 v, 200-mhz, 9-output clock driver document number: 38-07474 rev. ecn no. issue date orig. of change description of change ** 128104 07/07/03 rgl new data sheet *a 245393 see ecn rgl re-worded select function descriptions in table 2. *b 2904632 04/05/2010 kvm the existing part numbers are repl aced with new ones: cy29350axi and cy29350axit with package type cells: [32-pin tqfp, pb -free] [32-pin tqfp ? tape and reel, pb-free]. *c 3223621 04/12/2011 bash added ordering code definitions . added acronyms and units of measure . updated in new template. [+] feedback
document number: 38-07474 rev. *c revised april 12, 2011 page 13 of 13 spread aware is a trademark of cypress semiconductor. all products and company names mentioned in this document may be the trad emarks of their respective holders. cy29350 ? cypress semiconductor corporation, 2003-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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